RME’s SteadyClock technology guarantees an excellent performance in all clock modes. Its highly efficient jitter suppression refreshes and cleans up any clock signal.

Usually a clock section consists of an analog PLL for external synchronization and several quartz oscillators for internal synchronization. SteadyClock requires one quartz only, using a frequency not equalling digital audio. Modern circuit designs like hi-speed digital synthesizer, digital PLL, 800 MHz sample rate and analog filtering allow RME to realize a completely newly developed clock technology, right within the FPGA at lowest costs. The clock’s performance exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts quite fast compared to other techniques. It locks in fractions of a second to the input signal, follows even extreme varipitch changes with phase accuracy, and locks directly within a range of 28 kHz up to 200 kHz.
The further improved SteadyClock FS technology attenuates even lowest frequency jitter (>1 Hz), provides an even higher jitter suppression at lowest self-jitter, and uses a low phase noise quartz with jitter in the range of femto seconds. Thanks to the highly efficient jitter suppression, the AD- and DA-conversion always operates on highest sonic level, being completely independent from the quality of the incoming clock signal.

SteadyClock has been originally developed to gain a stable and clean clock from the heavily jittery MADI data signal (the embedded MADI clock suffers from about 80 ns jitter). Using the input sources of the ADI-2 DAC, SPDIF, ADAT or AES, you’ll most probably never experience such high jitter values. But SteadyClock is not only ready for them, it would handle them just on the fly.